The present invention relates to a semiconductor device having nonvolatile memory cells of multi-storage forms, wherein a structure called xe2x80x9ca so-called MNOS (Metal Nitride Oxide Semiconductor)xe2x80x9d or xe2x80x9cMONOS (Metal Oxide Nitride Oxide Semiconductor)xe2x80x9d is configured as a base, and electrons are trapped in nitride near the interface between nitride and oxide at physically different positions, thereby making it possible to perform the storage of multi-valued information, an IC card using the semiconductor device, and a method for manufacturing such a semiconductor device. The present invention also relates to, for example, a technology effective for application to a microcomputer for an IC card provided with a nonvolatile memory of a multi-storage form on an on-chip basis.
A nonvolatile memory cell having a MONOS structure has been described in U.S. Pat. No. 5,768,192. According to this, as illustrated in FIGS. 45(A) and 45(B), a gate oxide film 1 and a gate nitride film 2 are laminated on a semiconductor region, and a memory gate electrode 3, which constitutes a word line, is provided thereon. Further, signal electrodes 4 and 5 either of which serves as a source or drain electrode, are formed in the semiconductor region placed under the memory gate electrode. The present nonvolatile memory cell is capable of trapping electrons in the gate nitride film 2 near the interface with the gate oxide film 1 at physically different positions, thereby performing the storage of multi-valued information. The injection of electrons in nitride is carried out according to channel hot electron injection. When one attempts to inject hot electrons into the right end of the gate nitride 2 as shown in FIG. 45(A), the left signal electrode 5 is used as a source (source (W)), and the right signal electrode 4 is used as a drain (drain (W)). Further, a drain current is caused to flow so that the direction indicated by arrow W takes the direction of motion of electrons. Thus, the electrons in a channel are accelerated under a high electric field near the drain and thereby brought into hot electrons, followed by injection into the drain end of the gate nitride film 2. When it is desired to inject hot electrons into the left end of the gate nitride film 2 as shown in FIG. 45(B), the right signal electrode 4 is used as a source (source (W)) and the left signal electrode 5 is used as a drain (drain (W)), and electrons are moved in the direction indicated by arrow W.
When information stored at the right end of the gate nitride film 2 is read as shown in FIG. 45(A), the right signal electrode 4 is used as a source (source (R)) and the left signal electrode 5 is used as a drain (drain (R)), and the memory gate electrode 3 may be set to a select level. Since a depletion layer of a MOS transistor expands into the drain side, the switch state of the memory cell greatly depends on the state of a threshold voltage on the source side. Thus, when information stored at the left end of the gate nitride film 2 is read as shown in FIG. 45(B), the left signal nitride 5 and the right signal electrode 4 are respectively used as a source (source (R)) and a drain (drain (R)) so that the sources and drains are set contrary to FIG. 45(A), and the memory gate electrode 3 may be set to a select level. If an erase state in which the threshold voltage is lower than the gate select level, is taken, then electrons flow in the direction indicated by arrow R.
A plan view of one memory cell is illustrated in FIG. 45(C). F means a minimum processed size. FIG. 46(A) illustrates voltage-applied states necessary for an erase (e.g., electron discharge) operation based on word-line units, FIG. 46(B) illustrates voltage-applied states necessary for an erase operation based on a memory array batch, FIG. 46(C) illustrates voltage-applied states necessary for writing (e.g., injection of electrons), and FIG. 46(D) illustrates voltage-applied states necessary for reading, respectively. In FIGS. 46(A) through 46(D), portions indicated by elliptical circles affixed to the memory cells respectively means regions intended for writing, erasing and reading.
The prior art is not capable of performing writing in plural bit units. Namely, upon the write operation as illustrated in FIG. 46(C), a bit line 6 is supplied with 3V and a word line 7 is supplied with 6V to carry out hot electron injection. However, if an attempt to carry out byte writing, for example is made, then a write blocking or inhibition voltage of 6V must be applied to the corresponding bit line with respect to a write inhibition bit. In doing so, a large electric field occurs between the bit line and a word line write-unselected at 0V and hence writing is effected on an undesired bit. Since the channel hot-electron injection system is adopted, a write current will increase. Upon the read operation as shown in FIG. 46(D) as well, it is necessary to set a source line for an adjacent memory cell which shares the use of a bit line 6 between a memory cell selected for the read operation and the adjacent memory cell, to floating (F). There is a possibility that the read operation based on such a virtual ground system will be susceptible to the unbalance of parasitic capacity of the source line brought to the floating and the read operation will be unstable.
As one for solving some of the problems, there is known the preceding application (Unexamined Patent Publication No. 2001-156275, U.S. Ser. or application No. 09/660,923) filed by the present applicant. In a nonvolatile memory cell shown in the present application, as illustrated in FIG. 47(A), a gate oxide film 11 and a gate nitride film 12 are laminated on a semiconductor region, and a memory gate electrode 13, which constitutes a word line, is formed thereon. Further, switch gate electrodes 16 and 17 are formed over the semiconductor region on both sides of the memory gate electrode 13 with gate oxide films 14 and 15 interposed therebetween. Signal electrodes 18 and 19 either of which serves as a source or drain electrode, are formed in the semiconductor region lying in the neighborhood below the respective switch gate electrodes 16 and 17. Since the present memory cell is added with the switch gate electrodes 16 and 17, a cell size increases correspondingly as illustrated in FIG. 47(B). Erasing effected on the memory cell is carried out by applying an electric field between the word line (memory gate electrode) and a substrate and drawing electrons into the substrate as illustrated in FIG. 48(A). Writing is carried out by a source side hot-electron injection system. Namely, as illustrated in FIG. 48(B), a word line 20 for a write-selected memory cell is set to a high potential to allow a channel current to flow through the memory cell via an on-state switch gate electrode 16, whereby an electric field is formed between a memory gate electrode 13, and a substrate and a source electrode 18. Thus, when the electrons from the signal electrode 18 used as a source electrode pass through a channel narrowed down by the switch gate electrode 16, they are accelerated and set high in energy. They are further accelerated under a high electric field between the memory gate electrode and the substrate, followed by trapping into the gate nitride film 12 on the signal electrode 18 side used as the source electrode. Since the writing is carried out according to electron source side injection, the source/drain at reading may be the same as at writing. As shown in FIG. 48(C), a signal electrode 19 may be used as a drain and a signal line 21 may be used as a bit line. W in FIG. 47(A) means the direction of injection of electrons at writing, R means the direction of motion of electrons at a read operation, and E means the direction of transfer of electrons at erasure. Incidentally, when the electrons are injected into the gate nitride film 12 on the signal electrode 19 side although not shown in the drawing and thereby stored information is read, voltage conditions may be varied so that the source and drain are changed or reversed. Thus, when the electrons from the signal electrode 18 used as a source electrode pass through a channel narrowed down by the switch gate electrode 16, they are accelerated and set high in energy. They are further accelerated under a high electric field between the memory gate electrode and the substrate, followed by trapping into the gate nitride film 12 on the signal electrode 18 side used as the source electrode. Since the writing is carried out according to electron source side injection, the source/drain at reading may be the same as at writing. As shown in FIG. 48(C), a signal electrode 19 may be used as a drain and a signal line 21 may be used as a bit line. W in FIG. 48(C) means the direction of injection of electrons at writing, R means the direction of motion of electrons at a read operation, and E means the direction of transfer of electrons at erasure. Incidentally, when the electrons are injected into the gate nitride film 12 on the signal electrode 19 side although not shown in the drawing and thereby stored information is read, voltage conditions may be varied so that the source and drain are changed or reversed.
According to the memory cell structure of FIG. 47, since the switch gate electrodes 16 and 17 are provided, the separation of the corresponding memory cell from its adjacent memory cell sharing the use of the source line/bit line is allowed and the source line for the adjacent memory cell may not be set to the floating upon writing or reading. Since the writing is carried out according to the source side hot-electron injection, a write current can also be reduced.
However, the present inventors could find out the following points as a result of further discussions about the memory cell structure. Firstly, rewriting based on plural bit units like byte rewriting cannot be implemented. Namely, a bit line 6 and a word line 7 are respectively supplied with 3V and 6V upon a write operation as illustrated in FIG. 48(B) to perform source side electron injection. However, if an attempt to carry out byte writing, for example is made, then a write blocking or inhibition voltage 6V must be applied to the bit line with respect to a write inhibition bit, and a switch gate electrode which accepts it, must be controlled to a voltage higher than 6V. In doing so, a large electric field occurs between the bit line and a word line write-unselected at 0V, and hence electrons are undesirably injected or discharged with respect to each write-unselected memory cell. Secondly, in the source side electron injection system, electrons from the source side are injected into an insulating film like silicon oxide between a switch gate electrode and a gate nitride film, so that erase/write characteristics are degraded. Thirdly, it has been clearly found out that even the source side electron injection system increase in current consumption as compared with tunnel writing and needs further low power consumption upon application to an IC card or the like supplied with power in non-contact form. Fourthly, it has been clearly found out by the present inventors that because of a configuration using switch gate electrodes, the above memory cell increases in area as compared with each memory cell employed in the channel hot electron injection system, and there is need to provide new means for reducing a chip occupied area as a whole in terms of the layout of each memory cell and a well structure or the like.
An object of the present invention is to implement rewriting based on plural bit units like byte rewriting with respect to a memory using memory cells of multi-storage forms.
Another object of the present invention is to prevent electrons delivered from a source side from being injected into an insulating film between each of switch gate electrode and a gate nitride film and improve rewrite resistance characteristics.
A further object of the present invention is to reduce a write current produced from a source side of a memory cell of a multi-storage form.
A still further object of the present invention is to provide a semiconductor device like a microcomputer or a data processor most suitable for mounting to a non-contact IC card in terms of the consumption of power by an on-chip memory cell of a multi-storage form.
Further, the present invention aims to provide a method capable of relatively easily manufacturing a memory cell of a multi-storage form, which is capable of performing the byte rewriting and is excellent in rewrite resistance characteristics.
The above, other objects, and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
Summaries of typical ones of the inventions disclosed in the present application will be described in brief as follows:
[1]  less than  less than Memory cell structure and plural bits writing greater than  greater than  Each of nonvolatile memory cells of multi-storage forms, which are placed in a semiconductor device, has a configuration wherein a memory gate electrode (33) is formed over a first semiconductor region (30) with first and second gate insulating films (31, 32) interposed therebetween, first and second switch gate electrodes (36, 37) are formed over the first semiconductor region lying on both sides of the memory gate electrode with third gate insulating films (34, 35) interposed therebetween, and first and second signal electrodes (38, 39) each used a source or drain electrode, are formed in the first semiconductor region lying in the neighborhood below the respective switch gate electrodes, and the memory gate electrodes and the switch gate electrodes respectively extend in a first direction.
In the nonvolatile memory cell, the storage of information therein is carried out based on the difference in threshold voltage as viewed from the memory gate electrode according to the amount of carriers, e.g., electrons captured by the second gate insulating film, and the injection of the electrons is allowed according to the source side injection system. For instance, erasing for the nonvolatile memory cell is carried out by applying an electric field between the memory gate electrode and the first semiconductor region to thereby draw electrons from the second gate insulating film to the first semiconductor region. For example, writing is carried out according to the source side injection system. The memory gate electrode is brought to a high potential to allow a channel current to flow into the memory cell through the on-state switch gate electrode, whereby an electric field is formed between the memory gate electrode and the first semiconductor region and signal electrode used as the source. Thus, when the electrons from the signal electrode used as the source electrode pass through a channel narrowed down by the switch gate electrode, they are accelerated and increase in energy. Further, they are accelerated under a high electric field lying between the memory gate electrode and the first semiconductor region, whereby they are obtained by the second insulating film on the signal electrode used as the source electrode.
According to the memory cell structure, since the writing is carried out according to the source side injection, a write current can also be reduced.
In particular, the memory cell structure is adopted wherein the memory gate electrode and the switch gate electrodes are arranged in parallel in the same direction. Therefore, even if a write voltage is applied to the memory gate electrode common for the plurality of memory cells which use the memory gate electrode and switch gate electrodes in common, write and write blocking voltage states can be applied to the respective memory cells through their inherent first and second signal electrodes. If at this time, the switch gate electrodes of memory cells intended for write non-selection, each having the memory gate electrode and switch gate electrodes different from each memory cell intended for writing are respectively brought to a cut-off state, then the application of an undesired high electric field to the second gate insulating film for each memory cell for write non-selection can be blocked. Accordingly, writing can be carried out in units of plural memory cells like byte units.
Types of the storage of the information by the nonvolatile memory cell will be described. The single nonvolatile memory cell stores 2-bit information therein according to a first state (first write state) in which carriers, e.g., electrons are captured on the first switch gate electrode side of the second gate insulating film, a second state (first erase state) in which the electrons captured in the first state are reduced, a third state (second write state) in which electrons are captured on the second switch gate electrode side of the second gate insulating film, or a fourth state (second erase state) in which the electrons captured in the third state are reduced.
Since the threshold voltage of a MOS type transistor is principally placed under the influence of an electrical charge injected into the source side, the source/drain is changed with respect to each memory cell of the multi-storage form to perform a read operation, whereby 2-bit stored information can be obtained from one nonvolatile memory cell back and forth. This can be carried out in the following manner specifically. When a potential at the second signal electrode selected by the second switch gate electrode is set higher than a potential at the first signal electrode selected by the first switch gate electrode, the nonvolatile memory cell can read 1-bit storage information placed in the first or second state. When a potential at the first signal electrode selected by the first switch gate electrode is set higher than a potential at the second signal electrode selected by the second switch gate electrode, the nonvolatile memory cell can read 1-bit storage information placed in the third or fourth state.
[2]  less than  less than Memory cell array greater than  greater than  Attention is made to a memory cell array wherein a plurality of the nonvolatile memory cells (MC) are arranged in matrix form. In the memory cell array, the first and second signal electrodes have first and second signal wirings which are respectively connected thereto and extend in a second direction substantially orthogonal to the first direction. The first and second signal wirings are shared between a plurality of nonvolatile memory cells arranged in parallel in the second direction, and the memory gate electrode and switch gate electrodes are commonly used for a plurality of nonvolatile memory cells arranged in parallel in the first direction.
A pair of the nonvolatile memory cells which is adjacent to the first direction and shares the use of the memory gate electrode, may adopt a configuration wherein either one of the first and second signal electrodes is used in common and the others thereof are individualized, and the first and second signal electrodes are connected to their corresponding first and second signal wirings. Thus, the number of the signal wirings can be reduced. Further, this contributes to a reduction in chip occupied area of a memory cell array.
[3]  less than  less than Erase greater than  greater than  The first semiconductor region is configured as a well region. Thus, a plurality of the nonvolatile memory cells, which share the use of the memory gate electrode and the first and second switch gate electrodes, are disposed in a plurality of electrically-separated well regions (30m, 30n) in divided form, and each of the nonvolatile memory cells is caused to discharge electrons from the second gate insulating film to the corresponding well region according to the difference in potential between the well region and the memory gate electrode. Thus, electron emission like erasing for the memory cell can be carried out in well region units. If erasing is allowed in well units, then an erase operation is allowed for each byte according to well separation made for each byte. However, when the divided number of well regions increases, well separation regions relatively increase, so that a chip occupied area of a memory cell array increases.
In order to enable the erasing in small number of bit units even if the divided number of well regions is reduced, electrons may be emitted from the second gate insulating film to the first semiconductor region according to the difference in potential between the first or second signal electrode selected by the first or second switch gate electrode and the first semiconductor region. Thus, the erase operation can be carried out in a minimum unit corresponding to the first or second signal electrode.
In order to enable the erasing with the memory gate electrode as a minimum unit, electrons may be emitted from the second insulating film to the memory gate electrode according to the difference in potential between the corresponding signal electrode selected by the first or second switch gate electrode and the memory gate electrode.
[4]  less than  less than Low power consumption and improvement in rewrite resistance characteristics greater than  greater than  High-concentration impurity regions (60, 80) are respectively formed in the first semiconductor region placed below the first and second gate insulating films with widths less than or equal to width sizes of the corresponding insulating films. When the electrons are captured on the first switch gate electrode side or second switch gate electrode side of the second gate insulating film, the first semiconductor region is supplied with a backward substrate bias voltage (negative substrate bias voltage in the case of p-type first semiconductor region). Thus, a strong field occurs in the vertical direction (lamination direction) of the first and second gate insulating films in the high-concentration impurity regions, and holes are drawn into the first semiconductor region directly under the high-concentration impurity regions, so that secondary electrons are produced and injected into the second gate insulating film together with electrons supplied from the source. Thus, even if an electric field is low between a memory gate electrode and a source electrode, hot electrons can be produced in a short time and injected into the second gate insulating film. Thus, since a write current to be supplied from the corresponding bit line can be reduced, low power consumption can be promoted and a write time can also be shortened. Besides, since the electric field between the memory gate electrode and the source electrode is small, the probability that electrons will be injected from the source side to an insulating film between a switch gate electrode and the gate nitride film, is also lowered, and the resistance characteristics of rewriting of each memory cell are also improved. Since the high-concentration impurity regions are simply locally provided in the first semiconductor region under the second gate insulating film in particular, a substrate bias voltage can be applied to the first semiconductor region without degradation of junction withstand for the source and drain.
[5]  less than  less than Reduction in the number of sense amplifiers greater than  greater than  Since the threshold voltage of the MOS type transistor is principally placed under the influence of the electrical charge injected into the source side as described above, the source/drain is changed to perform a read operation, whereby 2-bit stored information can be obtained from one nonvolatile memory cell back and forth. From the viewpoint of the property that the source/drain is changed to perform the read operation, sense amplifiers for detecting read information may separately be provided in association with the first and second signal electrodes of each memory cell. Judging from the viewpoint of the reduction in chip occupied area, a configuration may be adopted wherein each sense amplifier shares the use of both the first and second signal electrodes of each memory cell. For example, the sense amplifiers are selectively switched and connected to the signal electrode used as the source upon the read operation. Alternatively, a first signal wiring is connected to the first signal electrode of the nonvolatile memory cell, a second signal wiring is connected to the second signal electrode of the nonvolatile memory cell. Further, a precharge circuit (53) capable of precharging the first signal wiring and the second signal wiring, a sense amplifier (50) which detects a change in the level of the first signal wiring, and a control circuit (54, 104) are provided. The control circuit may allow the precharge circuit to perform a precharge operation so that either the first signal electrode or the second signal electrode and the other thereof are respectively brought to a high potential and a low potential according to a read address, and cause the sense amplifier to detect the presence or absence of a change in the level of the first signal wiring after the completion of the precharge operation.
[6]  less than  less than IC card greater than  greater than  A semiconductor device on which the nonvolatile memory cells of multi-storage forms are mounted, can be implemented as a data processing LSI such as a microcomputer, a data processor or the like, a system LSI which implements system on-chip for particular application, or a nonvolatile memory LSI. When, for example, the data processing LSI such as the microcomputer or the data processor or the like is considered, the semiconductor device can comprise a memory circuit (MEM) provided with the nonvolatile memory cells as storage elements, a CPU (110) capable of accessing the memory circuit, and an external interface circuit (113) connected to the CPU, all of which are provided on a single semiconductor chip.
If such a semiconductor device is used as a microcomputer for an IC card, the IC card can comprise the semiconductor device, and a card interface terminal connected to the external interface circuit of the semiconductor device, all of which being provided on a card substrate. In the case of a non-contact IC card, an antenna is provided on the card substrate. For example, the transfer of power by an ac magnetic field and communications based on electromagnetic induction can be done in non-contact form. Alternatively, both the power transfer and the information communications may be carried out by the electromagnetic induction. Only the power transmission may be carried out in non-contact form.
[7]  less than  less than Manufacturing method of semiconductor device greater than  greater than  The invention according to an aspect of a method of manufacturing a memory device structure having high-concentration impurity regions in a first semiconductor region directly below a second gate insulating film in each of the nonvolatile memory cells of the multi-storage forms is roughly divided into a first manufacturing method for introducing a high-concentration impurity into a first semiconductor region with a memory gate electrode as a mask, and a second manufacturing method for introducing a high-concentration impurity into a first semiconductor region with switch gate electrodes as masks.
The first manufacturing method includes (a) a step of forming a first conductivity type (p-type) first semiconductor region (30) on a main surface of a semiconductor substrate, (b) a step of forming a first insulating film and a second insulating film on the main surface of the semiconductor substrate on the first semiconductor region in order, (c) a step of forming a first conductor element (memory gate electrode) having a first width as viewed in a first direction of the main surface of the semiconductor substrate and a second width as viewed in a second direction substantially orthogonal to the first direction, on the second insulating film, (d) a step of introducing a first impurity (p type: B) of the first conductivity type into the first semiconductor region below the first conductor element as viewed in the first direction to selectively form second semiconductor regions (high-concentration impurity regions 60), (e) a step of forming a third insulating film on side walls of the first conductor element as viewed in the first direction, (f) a step of forming second and third conductor elements (switch gate electrodes) respectively having a third width as viewed in the first direction and a fourth width as viewed in the second direction at both ends of the first conductor element as viewed in the first direction with the third insulating film interposed therebetween, and (g) a step of introducing a second impurity of a second conductivity type (n-type) opposite to the first conductivity type as viewed in the first direction to form a third semiconductor region (source/drain) within the first semiconductor region on the sides opposite to the first conductor element, of the second and third conductor elements.
The second semiconductor region forming step further includes a step of introducing a third impurity (n-type: As) of the second conductivity type into the first semiconductor region at both ends of the first conductor element. The third impurity may be ion-implanted at a first angle to the main surface of the semiconductor substrate, the first impurity may be ion-implanted at a second angle to the main surface of the semiconductor substrate, and the first angle may be set larger than the second angle. Thus, even if the second semiconductor regions used as the high-concentration impurity regions formed of the first impurity protrude outside from both ends in the first direction, of the first conductor element, the impurity concentration of the overflowing or protruded portion can be modified later, whereby the second semiconductor regions can be fabricated with high accuracy.
The second width of the first conductor element may be set greater than the first width, the fourth width of the second conductor element may be set greater than the third width, and the first and second conductor elements may extend in the second direction. Thus, the fabricated memory cells can be rewritten in plural bit units like the byte units as described above.
The first insulating film may comprise silicon oxide, and the second insulating film may comprise silicon nitride.
The second manufacturing method includes (a) a step of forming a first conductivity type (p-type) first semiconductor region (30) on a main surface of a semiconductor substrate, (b) a step of forming two first conductor elements (switch gate electrodes) having a first width as viewed in a first direction of the main surface of the semiconductor substrate and a second width as viewed in a second direction substantially orthogonal to the first direction, on the first semiconductor region with a predetermined interval interposed therebetween, (c) a step of forming a first insulating film on side walls of the first conductor element in a region between the first conductor elements, (d) a step of introducing a first impurity (p-type: B) of the first conductivity type within the first semiconductor region in the region lying between the first conductor elements and interposed by the first insulating film formed on the side walls of the first conductor element in order to form a second semiconductor region (high-concentration impurity region 80) therewithin, (e) a step of forming a second insulating film and a third insulating film over the surface of the semiconductor substrate in the region between the first conductor elements, (f) a step of forming a second conductor element (memory gate electrode) having a third width as viewed in the first direction and a fourth width as viewed in the second direction, on the third insulating film, and (g) a step of introducing a second impurity (n-type) of a second conductivity type opposite to the first conductivity type as viewed in the first direction to form a third semiconductor region (source/drain) within the first semiconductor region on the side opposite to the second conductor element, of the first conductor element.
In the second manufacturing method, the first insulating film forming step may include a step of depositing an insulating film on the semiconductor substrate, and a step of subjecting the insulating film to anisotropic etching and selectively leaving the insulating film on the side walls of the first conductor element.
The second conductor element may be formed on the side walls of the first conductor element with the third insulating film interposed therebetween. The second insulating film may comprise silicon oxide, and the third insulating film may comprise silicon nitride.
The second width of the first conductor element may be set greater than the first width, the fourth width of the second conductor element may be set greater than the third width, and the first and second conductor elements may extend in the second direction. Each of the memory cells fabricated in this way is capable of performing batch writing or the like in plural bit units like the byte units as described above.